sci-electronics/verilator

Verilator is the fastest free Verilog HDL simulator.

Versions

Slot Version Repository Platforms
0 3.908 scientific ~amd64 arm? armv7? armv8? ~x86

Metadata

Homepage http://www.veripool.org/wiki/verilator
Summary Verilator is the fastest free Verilog HDL simulator
Description It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
Dependencies (
    build:
    sys-devel/bison
    sys-devel/flex
    build+run:
    dev-lang/perl:*
)
Downloads http://www.veripool.org/ftp/verilator-3.908.tgz
Licences LGPL-3